The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a device isolation layer in a semiconductor device and a non-volatile memory device.
Semiconductor devices include a device isolation layer to electrically separate patterns from one another. A device isolation layer is generally formed through a shallow trench isolation process (STI).
The conventional STI process for forming a device isolation layer is performed as follows. First, a device isolation trench is formed by etching a substrate to a predetermined depth, and an insulation layer for forming a device isolation layer is formed over the substrate with the device isolation trench formed therein. Subsequently, a device isolation layer filling the substrate is formed by performing planarization until the substrate is exposed.
According to a conventional technology, an insulation layer is formed of a high density plasma (HDP) oxide to form a device isolation layer. Recently, however, there is a limitation in filling a device isolation trench with the HDP oxide due to the aspect ratio of the device isolation trench which is increasing according to the improvement in integrity of semiconductor devices.
To fill the device isolation trench without void, the conventional technology uses a flowable oxide to form the insulation layer for forming a device isolation layer. The flowable oxide is a material having a flowing property because it has a relatively low viscosity. A non-limiting example of the flowable oxide is perhydro-polysilazane (PSZ).
After filling the device isolation trench with the flowable oxide, a dense insulation layer for forming a device isolation layer may be formed through a thermal treatment. The thermal treatment eliminates gas components from the flowable oxide. To take an example, when a thermal treatment is performed after the formation of a PSZ layer, nitrogen or hydrogen inside the PSZ layer are ejected out in the form of NH3 gas or H2 gas. During the process, the chemical structure of the PSZ layer is changed into a SiO2 layer. In short, a device isolation layer formed of Spin On Dielectric (SOD).
In this way, it is possible to fill the device isolation trench with the insulation layer for forming a device isolation layer without void, no matter how high aspect ratio the device isolation trench has.
However, according to the above-described conventional technology, since the density of the flowable oxide is decided according to how much gas is ejected during the thermal treatment, the multiple insulation layers for forming a device isolation layer have different density. This leads to uneven etch rate among the multiple insulation layers for forming a device isolation layer. Accordingly, an effective field oxide height (EFH) difference occurs among device isolation layers.
In a case where device isolation layers are formed of SOD by using a PSZ layer, moat may be formed during a process of removing a hard mask layer formed over a substrate due to its higher etch rate than a conventional HDP oxide layer.
Meanwhile, a non-volatile memory device retains data stored therein even through power supply is cut off. Non-volatile memory devices are divided into a charge storage-type non-volatile memory device and a charge trap-type non-volatile memory device according to how data are stored.
The charge storage-type non-volatile memory device stores charges in a floating gate electrode to store data, whereas the charge trap-type non-volatile memory device stores data by trapping charges in a charge trap layer. Therefore, the qualities of a tunnel dielectric layer, which is provided as an energy barrier during the tunneling of charges, and a charge storage layer (or a charge trap layer), which stores (or traps) charges, are important in a non-volatile memory device.
Conventional methods for forming a device isolation layer of a non-volatile memory device may damage a tunnel dielectric layer and/or a charge storage layer (or a charge trap layer) during the formation of the device isolation layer. Particularly, when a device isolation layer is formed of an HDP oxide layer, the tunnel dielectric layer and/or a charge storage layer (or a charge trap layer) may be damaged during a plasma process for forming the HDP oxide layer. As a result, the data retention characteristic of the memory device may be deteriorated.